----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:42:01 09/17/2014 
-- Design Name: 
-- Module Name:    Random_Data_1bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Random_Data is
	 generic ( width : integer :=  6 ); 
    Port ( clk : in  STD_LOGIC;
           en : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR(width-1 downto 0));
end Random_Data;

architecture Behavioral of Random_Data is
signal locRand_num : STD_LOGIC_VECTOR(31 downto 0) := (31 => '0',others => '0');
signal locZeros : STD_LOGIC_VECTOR(width-1 downto 0) := (width-1 => '0',others => '0');

	component Random_32bit
		generic ( width : integer := 32);
		port(
		clk : in std_logic;
      random_num : out std_logic_vector (width-1 downto 0));
	end component;
	
begin

PseudoGen: Random_32bit
generic map(width => 32)
port map(
	clk => clk,
	random_num => locRand_num);

process (clk, en)
begin

	if (clk'event and clk = '1' and en = '1') then
		--data_out <= locRand_num(width-1 downto 0);
		data_out <= locRand_num(31 downto 32-width);
	else
		data_out <= locZeros;
	end if;
	
end process;


end Behavioral;